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1 ltc4212 4212f applicatio s u features typical applicatio u descriptio u n allows safe board insertion and removal from a live backplane n controls supply voltages from 2.5v to 16.5v n adjustable soft-start with inrush current limiting n fast turn-off time n no external gate capacitor is required n power good input with adjustable timer and glitch filter n power-up timeout circuit interfaces with external supply monitors n dual level overcurrent fault protection n automatic retry or latched mode operation n high side drive for an external n-channel fet n ms10 package the ltc ? 4212 is a hot swap tm controller that allows a board to be safely inserted and removed from a live backplane. an internal high side switch driver controls the gate of an external n-channel mosfet for supply voltages ranging from 2.5v to 16.5v. the ltc4212 provides soft- start and inrush current limiting during the start-up period. it features a power-up timeout circuit that discon- nects the system supply when the onboard supplies do not enter into regulation within an adjustable timeout period. the controller interfaces with external supply monitor ics or directly with the pgood pin of a dc/dc converter. after normal power-up, a programmable power good glitch filter can be enabled to filter out short term dips in the supplies. two current limit comparators provide dual level overcurrent circuit breaker protection. the slow com- parator trips at v cc C 50mv and activates in 18 m s. the fast comparator trips at v cc C 150mv and typically responds in 500ns. the ltc4212 can be configured for both latchoff and autoretry applications and is available in a 10-pin msop package. n electronic circuit breaker n hot board insertion and removal n self-isolating hot swap boards hot swap controller with power-up timeout , ltc and lt are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. + v cc sense ltc4212 10 f + 10 f 5v 2.5v 1.5a 3.3v 1.5a 4212 ta01a gate pgt pgf timer 0.01 f pgi on v cc 5v gnd z1 = smaj10a (tvs) 20k 10k 10 0.007 edge connector (male) si4410dy z1 10k 10k 2.1k 10k fault gnd fault + 10 f lt1963-2.5 4.7nf 270pf 100nf backplane connector (female) + 10 f + 10 f lt1963-3.3 ltc1727-2.5 gnd v cca v cc3 comp2.5 v cc25 comp3 comp a power-up waveforms on 5v/div timer 1v/div pgt 1v/div pgi 5v/div hot swap controller with power good function 5ms/div
2 ltc4212 4212f supply voltage (v cc ) ............................................... 17v input voltages on, pgi ................................................ C 0.3v to 17v sense .................................... C 0.3v to (v cc + 0.3v) timer, pgt, pgf ....................................C 0.3v to 2v output voltages gate ............................... internally limited (note 3) fault .................................................. C 0.3v to 17v operating temperature range ltc4212c .............................................. 0 c to 70 c ltc4212i ........................................... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c consult ltc marketing for parts specified with wider operating temperature ranges. absolute axi u rati gs w ww u package/order i for atio uu w (note 1) order part number ltc4212cms ltc4212ims ms part marking ltc5 ltc6 t jmax = 125 c, q ja = 200 c/ w 1 2 3 4 5 on timer pgt pgf gnd 10 9 8 7 6 fault v cc sense gate pgi top view ms package 10-lead plastic msop symbol parameter conditions min typ max units v cc v cc supply voltage range l 2.5 16.5 v i cc v cc supply current on = high, timer = low l 1 1.5 ma v lko internal v cc undervoltage lockout v cc low-to-high transition l 2.13 2.34 2.47 v v lkohst v cc undervoltage lockout hysteresis 110 mv i inon on input current v on = v cc or gnd 1 10 m a i leak fault leakage current v fault = 15v, pull-down device off l 0.1 2.5 m a i inpgi pgi pin input current v pgi = v cc or gnd 1 10 m a i insense sense input current v sense = v cc or gnd 1 10 m a v cb(fast) sense trip voltage (v cc C v sense ) fast comparator trips l 130 150 170 mv v cb(slow) sense trip voltage (v cc C v sense ) slow comparator trips l 40 50 60 mv i gateup gate pull-up current charge pump on, v gate 0.2v l C 12.5 C 10 C 7.5 m a i gatedown normal gate pull-down current on low l 130 200 270 m a fast gate pull-down current fault latched and circuit breaker 50 ma tripped or in uvlo, v gate = 15v d v gate external n-channel gate drive v gate C v cc (for v cc = 2.5v) l 4.0 8 v v gate C v cc (for v cc = 2.7v) l 4.5 8 v v gate C v cc (for v cc = 3.3v) l 5.0 10 v v gate C v cc (for v cc = 5v) l 10 16 v v gate C v cc (for v cc = 12v) l 10 18 v v gate C v cc (for v cc = 15v), (note 3) l 815v v gateov gate overvoltage lockout threshold l 0.08 0.2 0.3 v v onhi on threshold high l 1.23 1.316 1.39 v v onlo on threshold low l 0.4 0.455 0.5 v v pgi power good input threshold l 1.20 1.236 1.26 v v pgihst power good input hysterisis 28 mv the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v, unless otherwise noted. (note 2) electrical characteristics
3 ltc4212 4212f v pgfhi power good glitch filter high threshold l 1.20 1.236 1.26 v v pgfhst power good glitch filter hysterisis (note 4) 40 mv v pgthi power good timer high threshold l 0.928 0.952 0.976 v v pgtlo power good timer low threshold l 0.640 0.657 0.680 v v pgt d v power good timer delta threshold l 0.283 0.295 0.304 v i pgt power good timer pin current power good timer on, c pgt charging, pgt = 0.65v l C 5.61 C 5.1 C 4.59 m a power good timer on, c pgt discharging, pgt = 0.95v l 4.63 5.2 5.77 m a power good timer off, pgt = 1.5v 5 ma i pgf power good glitch filter pin current power good glitch filter on, c pgf charging l C 5.61 -5.1 C 4.49 m a power good timer off, pgf = 1.5v 5 ma i tmr timer current timer on, v timer = 1v l C 2.5 C 2 C 1.5 m a timer off, timer = 1.5v 5 ma v tmr timer threshold timer low to high l 1.20 1.236 1.26 v timer high to low l 0.15 0.200 0.40 v v fault fault threshold latched off threshold, fault high to low l 1.20 1.236 1.26 v v faulthst fault threshold hysteresis 50 mv v olfault output low voltage i fault = 1.6ma l 0.14 0.4 v t to power good time-out c pgt =10nf, pgt = 0.1v to fault low l 16.3 18.16 20 ms t faultlo power good input low at time-out to end of 14th pgt cycle 1 m s gate discharging t faultvg valid power good glitch to gate pgf > 1.26v 1.5 m s discharging t faultfc fast comp trip to gate discharging v cb = 0mv to 200mv step l 500 700 ns t faultsc slow comp trip to gate discharging v cb = 0mv to 100mv step l 10 18 30 m s t extfault fault low to gate discharging v fault = 5v to 0v l 135 m s t reset circuit breaker reset delay time on low to fault high l 120 250 m s t off turn-off time on low to gate off 10 m s the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v, unless otherwise noted. (note 2) electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all current into device pins are positive; all current out of device pins are negative; all voltages are referenced to ground unless otherwise specified. note 3: an internal clamp limits the gate pin to a minimum of 10v above v cc . driving this pin to voltages beyond the clamp may damage the part. if a lower gate pin voltage is desired, use an external zener diode. the gate capacitance must be < 0.15 m f at maximum v cc . note 4: guaranteed by design and not tested in production. symbol parameter conditions min typ max units
4 ltc4212 4212f typical perfor a ce characteristics uw gate voltage vs supply voltage v gate C v cc vs supply voltage gate voltage vs temperature v gate C v cc vs temperature supply current vs supply voltage supply current vs temperature undervoltage lockout threshold vs temperature supply voltage (v) 0 supply current (ma) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 16 4212 g01 4 8 12 20 14 2 6 10 18 temperature ( c) supply current (ma) 2.0 2.5 3.0 4212 g02 1.5 1.0 0 0.5 4.0 3.5 v cc = 16.5v v cc = 5v v cc = 2.5v C50 0 25 125 C25 50 75 100 temperature ( c) 2.0 undervoltage lockout threshold (v) 2.1 2.3 2.4 2.5 C25 25 50 4212 g03 2.2 C50 0 75 100 125 falling edge rising edge supply voltage (v) 0 gate voltage (v) 10 20 30 5 15 25 4 8 12 16 4212 g06 18 2 0 6 10 14 temperature ( c) C50 0 gate voltage (v) 5 15 20 25 0 25 125 4212 g07 10 C25 50 75 100 30 v cc = 16.5v v cc = 5v v cc = 2.5v supply voltage (v) 0 0 v gate C v cc (v) 2 6 8 10 12 14 16 18 4212 g08 4 246810 18 12 14 16 temperature ( c) 0 v gate C v cc (v) 2 6 8 10 75 18 4212 g09 4 0 25 C50 100 50 C25 125 12 14 16 v cc = 15v v cc = 3.3v v cc = 5v v cc = 12v specifications are t a = 25 c. v cc = 5v, unless otherwise noted. gate output source current vs supply voltage gate output source current vs temperature supply voltage (v) 7 gate output source current ( a) 9 11 13 8 10 12 4 8 12 16 4212 g10 20 2 0 6 10 14 18 temperature ( c) 7 gate output source current ( a) 8 10 11 12 C25 25 50 4212 g11 9 C50 0 75 100 125 13 v cc = 16.5v v cc = 2.5v v cc = 5v
5 ltc4212 4212f fast gate pull-down current vs supply voltage fast gate pull-down current vs temperature typical perfor a ce characteristics uw supply voltage (v) 20 fast gate pull-down current (ma) 40 60 80 30 50 70 4 8 12 16 4212 g14 18 2 0 6 10 14 temperature ( c) 20 fast gate pull-down current (ma) 30 50 60 70 C25 25 50 4212 g15 40 C50 0 75 100 125 80 specifications are t a = 25 c. v cc = 5v, unless otherwise noted. v cb (slow comp) vs supply voltage supply voltage (v) 0 v cb (slow comp) (mv) 52 56 60 16 4212 g26 48 44 50 54 58 46 42 40 4 2 8 6 12 14 10 18 v cb (fast comp) vs supply voltage slow comp trips to gate discharging delay vs supply voltage supply voltage (v) 0 v cb (fast comp) (mv) 170 165 160 155 150 145 140 135 130 16 4212 g28 4 8 12 18 14 2610 supply voltage (v) 0 slow comp trips to gate discharging delay ( s) 26 24 22 20 18 16 14 12 10 16 4212 g30 4 8 12 18 14 2610 fast comp trips to gate discharging delay vs supply voltage fast comp trips to gate discharging delay vs temperature slow comp trips to gate discharging delay vs temperature temperature ( c) slow comp trips to gate discharging delay ( s) 18 20 22 125 4212 g31 16 14 10 C25 25 75 C50 0 50 100 12 26 24 v cc = 16.5v v cc = 3v v cc = 5v v cc = 15v v cc = 12v supply voltage (v) 0 fast comp trips to gate discharging delay (ns) 600 500 400 300 200 100 0 16 4212 g32 4 8 12 18 14 2610 v cb = 0mv to 200mv step temperature ( c) fast comp trips to gate discharging delay (ns) 400 500 125 4212 g33 300 200 0 C25 25 75 C50 0 50 100 100 700 600 v cb = 0mv to 200mv step v cc = 16.5v v cc = 3v v cc = 12v v cc = 5v v cc = 15v power good timeout vs supply voltage supply voltage (v) 15 power good time-out (ms) 19 21 18 20 17 16 4 8 12 16 4212 g40 18 2 0 6 10 14
6 ltc4212 4212f typical perfor a ce characteristics uw specifications are t a = 25 c. v cc = 5v, unless otherwise noted. power good timeout vs temperature pgi low at timeout to gate discharging vs supply voltage pgi low at timeout to gate discharging vs temperature 15.0 power good time-out (ms) 18.0 19.0 20.0 17.5 18.5 19.5 17.0 16.5 16.0 15.5 4212 g41 temperature ( c) C25 25 50 C50 0 75 100 125 supply voltage (v) 0 pgi low at time-out to gate discharging (v) 1.8 1.5 1.2 0.9 0.6 0.3 16 4212 g44 4 8 12 18 14 2610 temperature ( c) 0.2 pgi low at time-out to gate discharging ( s) 2.0 C25 25 50 4212 g45 C50 0 75 100 125 0.4 0.8 1.2 1.4 1.8 0.6 1.0 1.6 pgf and pgt pin current (timer or filter off) vs supply voltage pgf and pgt pin current (timer or filter off) vs temperature 0 pgf and pgt current (timer or filter off) (ma) 10 9 8 7 6 5 4 3 2 1 4212 g51 temperature ( c) C25 25 50 C50 0 75 100 125 pgf pgt valid glitch to gate discharging vs temperature valid glitch to gate discharging vs supply voltage fault v ol vs supply voltage supply voltage (v) 1.30 valid glitch to gate discharging ( s) 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 4 8 12 16 4212 g52 18 2 0 6 10 14 0.5 valid glitch to gate discharging ( s) 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 4212 g53 temperature ( c) C25 25 50 C50 0 75 100 125 supply voltage (v) 0 fault v ol (v) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 16 4212 g54 4 8 12 18 14 2610 i ol = 5ma i ol = 1ma fault v ol vs temperature temperature ( c) pgf and pgt pin current (timer or filter off) (ma) 4 5 6 4212 g50 3 2 0 1 8 7 C50 0 25 125 C25 50 75 100 temperature ( c) vol (v) 0.20 0.25 0.30 4212 g55 0.15 0.10 0 0.05 0.40 0.35 C50 0 25 125 C25 50 75 100
7 ltc4212 4212f typical perfor a ce characteristics uw specifications are t a = 25 c. v cc = 5v, unless otherwise noted. fault pin low to gate discharging time vs temperature circuit breaker reset time vs supply voltage turn-off time vs supply voltage circuit breaker reset time vs temperature turn-off time vs temperature fault pin low to gate discharging time vs supply voltage supply voltage (v) 1.5 fault pin low to gate discharging time ( s) 2.5 3.5 4.5 2.0 3.0 4.0 4 8 12 16 4212 g58 18 2 0 6 10 14 temperature ( c) 1.5 fault pin low to gate discharging time ( s) 2.0 3.0 3.5 4.0 C25 25 50 4212 g59 2.5 C50 0 75 100 125 4.5 supply voltage (v) 80 circuit breaker reset time ( s) 120 160 200 100 140 180 4 8 12 16 4212 g60 18 2 0 6 10 14 temperature ( c) 80 circuit breaker reset time ( a) 100 140 160 180 C25 25 50 4212 g61 120 C50 0 75 100 125 200 supply voltage (v) 5 turn-off time ( s) 7 9 11 6 8 10 4 8 12 16 4212 g62 18 2 0 6 10 14 temperature ( c) 8.0 turn-off time ( s) 9.0 11.0 12.0 12.5 C25 25 50 4212 g63 10.0 8.5 10.5 11.5 9.5 C50 0 75 100 125 13.0
8 ltc4212 4212f uu u pi fu ctio s on (pin 1): on/off control input. the on pin is used to enable and disable ltc4212 operation and reset internal logic and the electronic circuit breaker (ecb). it must be pulled high (>1.316v) to start the first system timing cycle. if the on pin is pulled low (<0.455v typical) for more than 10 m s, the internal logic is reset and the gate pin is pulled down by a 200 m a current to turn off the external fet. if the on pin is pulled low for more than 120 m s, the electronic circuit breaker is reset. this pin is tied to a resistive divider in latch-off applications or to the fault pin and an external rc circuit in auto-retry applications. timer (pin 2): system timer input. an external capacitor (c timer ) connected from this pin to ground determines the duration of the first and second system timing cycles. the first timing cycle allows time for the board to be inserted properly. during the second timing cycle, a soft-start circuit controls the gate of the external n-channel fet to limit inrush currents from the backplane supply. pgt (pin 3): power good timer input. an external capaci- tor (c pgt ) connected from this pin to ground sets the power good time-out period. this is the maximum time allowed for externally monitored dc/dc converters to power-up into regulation and pull the pgi pin high. the nominal time-out cycle is 1.81s/ m f and begins from the end of the second system timing cycle. this pin is pulled to ground by an internal switch when the power good timer is disabled or when the ecb is tripped. pgf (pin 4): power good glitch filter input. an external capacitor (c pgf ) connected from this pin to ground deter- mines the power good glitch filter delay. the glitch filter is enabled if the externally monitored dc/dc converters are powered up within the power good time-out period (see pin 3). if the pgi pin goes low for longer than the filter delay, the ecb is tripped. gnd (pin 5): device ground connection. connect this pin to the systems analog ground plane. pgi (pin 6): power good input pin. this pin is used by the power good circuit to sense the open drain rst output or comparator outputs of an external supply monitor ic or the pgood output of a dc/dc converter. it requires an external pull-up resistor to a voltage above the v fault threshold 1.236v. when the power good timer times out (see pin 3), pgi must be high to avoid tripping the ecb and to enable the power good glitch filter. gate (pin 7): gate output pin. the output signal at this pin is the high side gate drive for the external n-channel fet pass transistor. as shown in the block diagram, an internal charge pump supplies a 10 m a gate current and sufficient gate voltage to drive the external fet for supply voltages from 2.5v to 16.5v. the internal charge pump and zener clamps at the charge pump output determine the gate drive voltage ( d v gate = v gate C v cc ). the charge pump produces a minimum 4v of d v gate for supplies in the range of 2.5v < v cc < 4.75v. for v cc > 4.75v, the d v gate is limited by zener clamp z1 connected between the charge pump output and the v cc pin. the d v gate is typically at 12v and with guaranteed minimum value of 10v. for v cc > 15v, the zener clamp z2 sets the limitation for d v gate . z2 clamps the gate voltage to ground to 28v typically. the minimum z2s clamp voltage is 23v. this effectively sets d v gate to 8v minimum. sense (pin 8): circuit breaker set pin. with a sense resistor placed in the power path between v cc and sense, the ltc4212s electronic circuit breaker trips if the voltage across the sense resistor exceeds the thresholds set internally for the slow comp and the fast comp, as shown in the block diagram. the threshold for the slow comp is v cb(slow) = 50mv, and the electronic circuit breaker trips if the voltage across the sense resistor exceeds 50mv for 18 m s. under transient conditions where large step current changes can and do occur over shorter periods of time, a second (fast) comparator instead trips the electronic circuit breaker. the threshold for the fast comp is set at v cb(fast) = 150mv, and the circuit breaker trips if the voltage across the sense resistor exceeds 150mv for more than 500ns. to disable the electronic circuit breaker, connect the v cc and sense pins together. v cc (pin 9): this is the positive supply input to the ltc4212. the ltc4212 operates from 2.5v < v cc < 16.5v, and the supply current is typically 1ma. an internal undervoltage lockout circuit disables the device until the voltage at v cc exceeds 2.34v.
9 ltc4212 4212f uu u pi fu ctio s C + C + + C + C slow comp 50mv 150mv 0.2v comp7 m3 18 s glitch filter uvlo C + fast comp 500ns delay bg v ref = 1.236v 0.2v cb trips or uvlo on low >10 s start-up current regulator gate charging 200 a10 a cb trips v ref 10 a 7 gate 8 sense 9 v cc charge pump z1 v z (typ) = 12v m2 gnd 5 fault 10 C + 4212 bd C + C + comp3 t timer 0.2v v ref comp4 normal timer 2 on 1 2 a m6 v cc m5 comp6 z2 v z (typ) = 28v v cc 1.316v 0.455v 1.5 s delay v ref 4 pgf C + comp5 m12 m9 m8 3 pgt C + comp9 m1 m10 5 a 5 a 5 a v ref 0.65v 0.95v disable glitch filter valid glitch disable timer 6 pgi + C comp8 + C + C comp2 comp1 logic 10 s 120 s 200 a gate pulldown reset ecb 0.95v 0.65v block diagra w fault (pin 10): open drain fault output or external fault input. if the fast comp, slow comp or the power good circuit trips the ecb, the fault pin is latched low. the fault pin is an open drain output and is typically connected by a 10k pull-up resistor to v cc . an external circuit can also trip the ecb by driving fault below 1.236v (typical).
10 ltc4212 4212f figure 1. on pin sets the undervoltage lockout voltage externally 3.3v r1 10k r2 10k on pin (a) v cc = 3.3v 5v r1 20k r2 10k on pin (b) v cc = 5v 12v r1 61.9k r2 10k on pin (c) v cc = 12v 4212 f01 hot circuit insertion when circuit boards are inserted into or removed from live backplanes, the supply bypass capacitors can draw huge transient currents from the backplane power bus as they charge. the transient current can cause permanent dam- age to the connector pins as well as cause glitches on the system supply, causing other boards in the system to reset. the ltc4212 is designed to turn a printed circuit boards supply voltages on and off in a controlled manner, allow- ing the circuit board to be safely inserted or removed from a live backplane. output voltage monitor unlike other ltc hot swap controller products, the ltc4212 does not have an fb pin and monitors onboard dc/dc converters via an external power supply monitor ic such as the ltc1326-2.5 or the ltc1727. this allows several dc/dc converters to be monitored at the same time. the ltc4212s pgi or power good input pin is used to monitor the rst or comparator outputs of the monitor ic and it can also be tied directly to the pgood pin of a dc/dc converter. undervoltage lockout the ltc4212s internal power-on reset circuit initializes the start-up procedure and ensures the ic is in the proper state if the input supply voltage exceeds 2.34v. if the supply voltage falls below 2.23v, the ltc4212 is in undervoltage lockout (uvlo) mode, and the gate pin is pulled low. since the uvlo circuitry uses hysteresis, the ltc4212 restarts after the supply voltage rises above 2.34v and the on pin goes high. in addition, users can utilize the on comparator (comp1) or the fault comparator (comp6) to effectively set up a higher undervoltage lockout level. figure 1 shows the external resistive divider for the on pin to adjust the systems undervoltage lockout voltage. the system will enter the plug-in cycle after the on pin rises above 1.316v. the resistive divider sets the circuit to turn on when v cc reaches around 79% of its final value. if a different turn on v cc voltage is desired change the resistive divider ratio accordingly. the fault comparator can also be used to set a higher undervoltage lockout voltage. if the fault comparator is used for this purpose, the system will wait for the input voltage to increase above the level set by the user before starting the second timing cycle. also, if the input voltage drops below the set level in normal operating mode, the electronic circuit breaker (ecb) trips and the user must cycle the on pin or v cc to restart the system. operatio u system timing system timing for the ltc4212 is generated by the timer circuitry (see the block diagram). if the ltc4212s inter- nal timing circuit is off, an internal n-channel fet connects the timer pin to gnd. if the timing circuit is enabled, an internal 2 m a current source is then connected to the timer pin to charge c timer at a rate given by equation 1: c charge -up rate timer = m 2a c timer (1) when the timer pin voltage reaches comp4s threshold of 1.236v, the timer pin is reset to gnd. equation 2 gives an expression for the timer period: tv c a timer timer = m 1 236 2 . (2) as a design aid, the ltc4212?s timer period as a function of the c timer using standard values from 3.3nf to 0.33 m f is shown in table 1. the c timer value is vital to ensure a proper start-up and reliable operation. this timing period should not be exces- sive as an output short can occur at start-up causing the external mosfet to overheat. a good starting point is to
11 ltc4212 4212f set c timer = 10nf and adjust its value accordingly to suit the specific applications. table 1. t timer vs c timer c timer t timer 0.0033 m f 2.0ms 0.0047 m f 2.9ms 0.0068 m f 4.2ms 0.0082 m f 5.1ms 0.01 m f 6.2ms 0.015 m f 9.3ms 0.022 m f 13.6ms 0.033 m f 20.4ms 0.047 m f 29.0ms 0.068 m f 42.0ms 0.082 m f 50.7ms 0.1 m f 61.8ms 0.15 m f 92.7ms 0.22 m f 136ms 0.33 m f 204ms power-up timeout circuit the power-up timeout circuit has two functions. during power-up, it trips the circuit breaker if the dc/dc convert- ers on the board do not power-up and do not enter regulation on time. after normal power-up, it is configured to trip the circuit breaker if any of the converters exit regulation for longer than a programmable delay. once the circuit breaker is tripped, the ltc4212 is latched off and the board is disconnected from the system supply. the on pin must be taken low for 120 m s to reset the circuit breaker and then high to reconnect the board to the backplane supply. the power-up timeout circuit uses three pins: pgi or power good input pin, pgt or power good timer pin and pgf or power good filter pin. it is enabled at the end of the second system timing cycle, provided that the fault pin is high. prior to being enabled or if fault is low, the pgt and pgf pins are pulled to gnd by internal n-channel fets, m5 and m12 respectively. when enabled, the power-up timeout circuit starts the power good timer, which generates a time-out period before the pgi pin is sampled. operatio u power good timer the timer consists of comp9, m8-m12, two 5 m a current sources and 0.65v and 0.95v threshold voltages for comp9. the pgi pin is normally connected to the rst output pin or comparator outputs of an external supply monitor ic or to the pgood pin of a dc/dc converter and drives a comparator, comp8 which has a threshold voltage of 1.236v and 28mv of hysterisis. the rst and pgood pins are typically open drain pins and require an external pull- up resistor. the upper end of the resistor must be con- nected to a voltage greater than the upper threshold of the pgi comparator (1.236v). a capacitor, c pgt , connected from the pgt pin to ground programs the time-out period generated by the power good timer according to equation 3. table 2 shows the power good time-out periods for a list of standard capaci- tor values. t timeout = 1.81 w ? c pgt (3) two 5 m a current sources are switched in and out to charge and discharge c pgt between 0.65v and 0.95v for 14 cycles. table 2. t timeout vs c pgt c pgt t timeout 3.3nf 5.97ms 4.7nf 8.51ms 6.8nf 12.3ms 8.2nf 14.8ms 0.01 m f 18.1ms 0.022 m f 39.8ms 0.033 m f 59.7ms 0.047 m f 85.1ms 0.068 m f 123ms 0.082 m f 148ms 0.1 m f 181ms 0.22 m f 136ms 0.33 m f 398ms 0.47 m f 851ms 0.68 m f 1230ms 0.82 m f 1480ms 1 m f 1810ms
12 ltc4212 4212f since the pgt is pulled to gnd by m12 before the power good circuit is enabled, the first positive ramp at the pgt pin starts from 0v instead of the 0.65v for the subsequent 13 cycles. power good time-out at the end of the time-out period, the pgi pin is sampled. m12 is turned on to discharge c pgt to ground. if the pgi pin is low when sampled, the dc/dc converters have not entered into regulation on time and the power good circuit trips the circuit breaker to latch off the board. if pgi is high when sampled, the converters powered up into regulation on time and the board is left powered up. the power good glitch filter is enabled and it monitors the pgi pin for a low, an indication that at least one dc/dc converter has dropped out of regulation. the glitch filter rejects low pulses shorter than a programmable period. power good glitch filter a glitch filter consisting of comp5, m5 and a 5 m a current source rejects pgi low pulses that are shorter than the duration programmed by an external capacitor, c pgf , connected from the pgf pin to gnd. once the glitch filter is enabled, m5 is switched off whenever pgi goes low. this allows an internal 5 m a current source to charge the capacitor at the pgf pin. if pgi stays low for long enough, the voltage at the pgf pin rises above the upper threshold of comp5 (1.236v) and causes the power good circuit to trip the circuit breaker. for a given c pgf capacitance connected between pgf and gnd, the minimum low pgi pulse width needed to trip the circuit breaker is given by: t pgf = 1.236v ? (c pgf )/5 m a + 5 m s (4) an internal 5pf capacitor and stray msop-10 package capacitance sets t pgf to 5 m s nominal when c pgf is omit- ted. table 3 shows t pgf values for various standard capacitors. tying the pgf pin to ground prevents the power good glitch filter from tripping the circuit breaker after normal power-up. operatio u table 3. t pgf vs c pgf c pgf t pgf 5 m s 10pf 7.5 m s 22pf 10.4 m s 33pf 13.2 m s 47pf 16.6 m s 68pf 21.8 m s 82pf 25.2 m s 100pf 29.7 m s 220pf 59.3 m s 330pf 86.6 m s 470pf 121.2 m s 680pf 173 m s 820pf 208 m s 1nf 252 m s soft-start or inrush current control the ltc4212 monitors the load current by sensing the voltage (v cc C v sense ) developed across an external sense resistor (r sense ) connected between the v cc and sense pins. during the second timing cycle (see normal operating sequence) a soft-start circuit turns on the external n-channel fet gradually to keep inrush currents in check. the soft-start circuit monitors and servos the voltage across r sense to 50mv by either connecting a 10 m a pull-up current source to the gate pin when the voltage across r sense is less than 50mv or discharging it with a 10 m a pull-down current source when the voltage rises above 50mv. therefore, the inrush current from the backplane supply is limited to: i limit(softstart) = 50mv/r sense (5) for example, i limit(softstart) = 5a when r sense = 0.01 w . assuming that the voltage across the sense resistor does not exceed 50mv, the voltage at the gate pin rises at rate given by: v gate slew rate = dv gate /dt =10 m a/c gate (6) where, c gate = power mosfet gate input capacitance (c iss ). for example, an si4410dy (a 30v n-channel power mosfet) exhibits an approximate c gate of 3300pf at
13 ltc4212 4212f operatio u v gs = 10v. from equation 6, the slew rate is calculated to be 3.03v/ms. the inrush current being delivered to the load while the gate pin is ramping depends on c load and c gate . the external n-channel mosfet acts as a source follower so that its source (load) voltage ramps up at the same rate as the gate pin. the output current component for capacitor charging is given by equation 7: i inrush = c load ? dv gate /dt (7) =10 m a ? c load /c gate where, c load is the total capacitance at the load side of the mosfet. for example, if c gate = 3300pf and c load = 2000 m f, the inrush current charging c load is 6.06a. note that the soft-start circuit will servo the inrush to i limit(softstart) or 5a in this example and dv gate /dt will be lower than calculated from equation 6. frequency compensation at soft-start if the external mosfets gate input capacitance (c iss ) is greater than 600pf, no external gate capacitor is required at gate to stabilize the internal current-limiting loop during soft-start. otherwise, connect a gate capacitor between the gate pin and ground to increase the total gate capacitance to be equal to or above 600pf. the servo loop that controls the external mosfet during current limiting has a unity-gain frequency of about 105khz and phase margin of 80 for external mosfet gate input capaci- tances of up to 2.5nf. electronic circuit breaker the ltc4212 features an electronic circuit breaker func- tion that protects against supply overvoltage, externally- generated fault conditions, shorts or excessive load current conditions and power good faults. if the circuit breaker trips, the gate pin is immediately pulled to ground, the external n-channel mosfet is quickly turned off and fault is latched low. the circuit breaker trips whenever the voltage across the sense resistor exceeds two different levels, set by the ltc4212s slow comp and fast comp thresholds (see block diagram). the slow comp trips the circuit breaker if the voltage across the sense resistor (v cc C v sense = v cb ) is greater than 50mv for 18 m s. the fast comp trips the circuit breaker to protect against fast load overcurrents if the transient voltage across the sense resistor is greater than 150mv for 500ns. the timing diagram of figure 2 illustrates when the ltc4212s electronic circuit breaker is armed. after the first timing cycle, the ltc4212s fast comp is armed at time point 6. this ensures that the system is protected against a short-circuit condition during the second timing cycle after c load has been fully charged. at time point 8, slow comp is armed when the internal control loop is disengaged. the timing diagram in figure 4 illustrates the operation of the ltc4212 when the load current conditions exceed the threshold of slow comp (v cb(slow) > 50mv). circuit breaker reset referring to the block diagram, the on pin drives two internal comparators, comp1 and comp2. comp1 is referenced to 1.236v and has a hysterisis of 80mv. comp2 is referenced to 0.5v and has a hysterisis of 45mv. the outputs of the two comparators drive an internal flip- flop to generate a typical high and low on pin threshold of 1.31v and 0.455v respectively. if the voltage at the on pin is driven below 0.455v for more than 10 m s, all internal control logic except the circuit breaker is reset. a 200 m a pull-down current source is connected to the gate pin to pull it down gradually. holding the on pin below 0.455v for 120 m s or longer, resets the circuit breaker. following reset, the on pin must be taken above 1.316v to start a power-up sequence. normal operating sequence figure 2 illustrates the normal power-up sequence for two different applications. the pgi (rst) and pgf (rst) waveforms are valid for applications which use the pgi pin to monitor the rst output of a supply monitor ic. the pgi (pgood) and pgf (pgood) waveforms refer to applica- tions that tie the pgi pin to the pgood output of a dc/dc converter. all other waveforms in figure 2 are common to both applications. the pgi and pgf waveforms for applications that connect pgi pin to the
14 ltc4212 4212f figure 2. normal power-up, power good glitch filter and ecb reset sequences check for gate < 0.2v on goes low glitch filter trips breaker check for fault high logic reset (200 a gate pulldown) fast comp armed slow comp & power good circuit armed pgi sampled circuit breaker reset v cc v cc on v ref 2v to 34v v ref timer gate dc/dc converter output fault pgt pgi (rst) pgf (rst) pgi (pgood) pgf (pgood) 4212 f02 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 power good time-out cycle (c pgt ) normal power-up sequence power good glitch filter sequence ecb reset sequence 200ms monitor delay 0.95v 0.65v 1st timing cycle (c timer ) 1st timing cycle (c timer ) 2nd timing cycle (c timer ) soft-start active 1.236v 1.236v operatio u
15 ltc4212 4212f applications where pgi monitors the rst output of a supply monitor like the ltc1326-2.5, the rst and there- fore the pgi pins are held low for another 200ms until time point 11 (see pgi (rst) waveform). at time point 12, the power good circuit samples the pgi pin. during normal power-up, pgi will go high before time point 12. the power good circuit disables and resets the power good timer and m12 is turned on to pull pgt to ground. the power good glitch filter is then enabled to monitor the pgi pin. power good glitch filter sequence the power good glitch filter sequence is also shown in figure 2 from time points 12 through 16. when the glitch filter is enabled, m5, the internal n-channel fet that shorts the pgf pin to gnd is switched off whenever pgi is low. this allows the c pgf capacitor to be charged by an internal 5 m a current source towards 1.236v. if the pgf pin voltage exceeds 1.236v, the power good circuit trips the circuit breaker to latch the part off. tying pgf to gnd disables the glitch filter and prevents the power good from tripping the circuit breaker after time point 12. for supply monitors such as the ltc1326-2.5, the glitch filter is less useful. the comparators in the ltc1326-2.5 that monitor the dc/dc converters have a typical propaga- tion delay of 13 m s. if any of the monitored supplies leave regulation for more than 13 m s, the rst signal will be pulled low until 200ms after all the supplies re-enter regulation. the net effect is that the ltc1326-2.5 per- forms the glitch filtering and rejects pulses shorter than 13 m s. the pgood output of a dc/dc converter does not have the 200ms delay of the ltc1326-2.5. thus any low pgood pulse will immediately cause c pgf to be charged towards 1.236v (time points 13 and 14). c pgf values can be selected to reject low pulses that are shorter than some desired pulse width. some supply monitor ics such as the ltc1727 provide access to the outputs of comparators monitoring the dc/dc converters as well as the rst output. the comparator outputs track the converter output voltages. if the ltc4212 pgi pin is used to monitor the output of a comparator rather than the rst output of the ltc1727, c pgf can be selected to reject low pulses shorter than a desired pulse width. comparator outputs of a supply monitor such as the ltc1727 are similar to pgi (pgood) and pgf (pgood). first timing cycle when the pc board makes contact with the backplane (time point 1), v cc starts to rise. while v cc < 2.23v, the ltc4212 is in uvlo mode. the gate pin is pulled to ground by a 200 m a current source to shut off the external n-channel mosfet and the timer, pgt and pgf pins are all pulled low by internal n-channel fets m6, m5 and m12. when v cc rises above the uvlo threshold of 2.34v (time point 2), the ltc4212 waits for the on pin to go high ( > 1.316v) and checks that the gate is low (v gate < 0.2v) before initiating the first timing cycle (time point 3). the first timing cycle begins with the timer pin up at a rate given by equation 1. at time point 4 (the timing period programmed by c timer ), the timer pin voltage equals v tmr = 1.236v. next the timer pin is pulled down by m6 to time point 5 where v tmr = 0.2v. at time point 5, the ltc4212 checks that the fault pin voltage is high (v fault > 1.236v) before initiating the second timing cycle. if fault is forced low externally, the second timing cycle will not start and the external n-channel fet stays off. second timing cycle at the beginning of the second timing cycle (time point 6), the ltc4212 fast comp is armed and the soft-start circuit is enabled. the gate pin is ramped up at a rate given by equation 6. if the inrush current from the backplane supply (equation 7) is large enough to cause the voltage drop across the sense resistor to exceed 50mv, the soft- start circuit activates to regulate the inrush current (equa- tion 5). the soft-start circuit continues to operate until time point 8 when the timer pin voltage equals v tmr = 1.236v again. at time point 8, slow comp is armed and the power good circuit is enabled. when the power good circuit is enabled, m12, the internal n-channel fet shorting the pgt pin to ground is switched off and the power good timer started. the dc/dc convert- ers enter regulation at time point 10. in applications where the pgi pin is connected to the pgood pin of a dc/ dc converter, pgi is pulled high shortly after the converter enters into regulation (see pgi (pgood) waveform). in operatio u
16 ltc4212 4212f 150mv, slow comp trips the ecb (time point 10). if the voltage across r sense jumps above 150mv for 500ns or more, fast comp will trip the ecb. when the ecb trips, the gate pin is driven to gnd immediately to shut off the external n-channel fet and disconnect the board from the backplane supply. the fault pin is latched to a low state and the power good circuit is reset. the pgt and pgf pins are shorted to ground by internal n-channel fets. in order to reset the fault latch, the on pin must be taken low for more than 120 m s (time points 12 to 14). after that, taking the on pin high (time point 15) starts a new power-up sequence. autoretry sequence once the circuit breaker trips, the ltc4212 can be config- ured to autoretry that is attempt to reconnect the backplane supply automatically. both fault and on pins are tied together to an external pull-up resistor to v cc (r auto ) and to a delay capacitor (c auto ) as shown in figure 5. figure 6 shows two autoretry sequences caused by a persistent short. when the circuit breaker trips (time point 9), an internal n-channel fet at the fault pin is turned on to pull the pin low. this discharges the autoretry capacitor, c auto towards ground. when the on pin volt- age drops below 0.455v for 10 m s (from time point 10), internal logic is reset and a 200 m a current source is connected to the gate pin. the gate pin is already pulled down to ground at time point 9. the circuit breaker is not reset so that the fault pin continues to discharge c auto . after the on pin has dropped below 0.455v for more than 120 m s (time point 11), the circuit breaker is reset. the n-channel fet at the fault pin is switched off and the pull-up resistor at the on pin starts to charge c auto towards the upper 1.316v threshold of the on pin. once the on pin voltage rises above 1.316v, the first timing cycle is started. the total cooling off period for the external n-channel fet starts at time point 9 when the circuit breaker trips to time point 15 when the second timing cycle is started. operatio u electronic circuit breaker (ecb) reset sequence the ecb reset sequence is shown in figure 2 from time points 17 through 19. at time point 17, the on pin is taken low. ten microseconds later at time point 18, the internal logic is reset and a 200 m a source is connected to the gate pin to pull the pin to ground. 120 m s after on goes low (time point 19), the ecb is reset. when the on pin is taken high at time point 20 a new first timing cycle is started. if the time from time point 17 to time point 18 is less than 120 m s, the ecb is not reset and taking the on pin high at time point 20 will not start a new first timing cycle. power good timeout fault sequence figure 3 shows a power-up sequence in which the dc/dc converters do not enter regulation on time and the power good trips the ecb. the sequence is the same as for the normal power-up in figure 2 until time point 12 when the power good timer times out and the pgi pin is sampled. since pgi is low, the power good circuit trips the ecb. the gate pin is pulled to ground immediately to disconnect power to the board and the fault pin is latched to a low state. the pgt and pgf pins are pulled to gnd internally by n-channel fets. to reconnect the board to the backplane supply, the on pin must be taken low for at least 120 m s to reset the ecb and then high again to start a new first timing cycle. overcurrent fault sequence figure 4 shows a power-up sequence with slow comp tripping the ecb. at the beginning of the second timing cycle (time point 6), the gate pin is connected to the soft- start circuit and fast comp is armed but it does not usually trip the ecb due to the action of the soft-start circuit on the gate pin. the soft-start circuit regulates the voltage across the r sense resistor to 50mv. at time point 8, the soft-start circuit is disconnected. a 10 m a current source pulls the gate pin up and slow comp is armed. if a short occurs and the voltage across r sense jumps above 50mv for more than 18 m s but is less than
17 ltc4212 4212f figure 3. power good time-out fault and ecb reset sequence check for gate < 0.2v on goes low check for fault high logic reset (200 a gate pulldown) fast comp armed slow comp & power good circuit armed pgi sampled circuit breaker reset v cc v cc on v ref 2.34v v ref v ref timer gate dc/dc converter output (rst) dc/dc converter output (pgood) fault pgt pgi pgf 4212 f03 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 power good time-out cycle (c pgt ) power good timeout fault sequence ecb reset sequence < 200ms 0.95v 0.65v 1st timing cycle (c timer ) 2nd timing cycle (c timer ) soft-start active v out v out operatio u
18 ltc4212 4212f operatio u figure 4. power-up with overcurrent, slow comparator trips the circuit breaker v cc v cc on v ref 2.34v v ref timer gate dc/dc converter output v cc ?v sense fault pgt pgi pgf 4212 f04 12 3 4 5 6 7 8 9 10 11 13 12 1415 16 power good timer enabled (c pgt ) 0.95v 0.65v 2nd timing cycle (c timer ) 1st timing cycle (c timer ) 1st timing cycle (c timer ) soft-start active v ref v cc ?v sense = 50mv > 50mv, >18 s it consists of the time the fault pin takes to discharge c auto (time points 9 to 10), the 120 m s needed to reset the circuit breaker (time points 9 to 11), the time it takes the pull-up resistor at the on pin to charge c auto above 1.316v (time points 11 to 12) and the elapsed time before the external n-channel starts to conduct during the second timing cycle (time points 12 to 16). sense resistor considerations the fault current level at which the ltc4212s internal electronic circuit breaker trips is determined by a sense resistor connected between the ltc4212s v cc and sense pins and two separate trip points. the first trip point is set
19 ltc4212 4212f operatio u figure 5. ltc4212 autoretry application + v cc sense ltc4212 9 1 10 23 87 10 f + 10 f 2 3 1 5v 2.5v 1.5a 3.3v 1.5a 4212 f05 6 gate pgt 4 pgf timer c timer 0.01 f pgi on v cc 5v gnd z1 = smaj10a (tvs) r auto 1m r x 10 r sense 0.007 edge connector (male) m1 si4410dy z1 r4 10k r6 2.1k r5 10k r g 100 fault gnd + 10 f lt1963-2.5 c pgt 180nf c pgf 18pf c x 10nf backplane connector (female) 5 + 10 f 2 3 1 + 10 f lt1963-3.3 4 3 ltc1326-2.5 gnd v cca 1 v cc3 6 rst 2 v cc25 c auto 2 f figure 6. autoretry sequence v cc on v ref 2.34v timer gate dc/dc converter output v cc C v sense fault pgt pgi pgf 4212 f06 12 3 456 78 10 9 11 12 131415 16 17 18 19 power good timer enabled (c pgt ) power good timer enabled (c pgt ) 0.95v 0.65v 0.95v 0.65v 2nd timing cycle (c timer ) 1st timing cycle (c timer ) 1.316v 1.31v 0.455v 0.455v 2nd timing cycle (c timer ) 1st timing cycle (c timer ) soft-start active soft-start active v ref v ref v ref v cc C v sense = 50mv v cc C v sense = 50mv > 50mv, > 18 s > 50mv, > 18 s
20 ltc4212 4212f operatio u by the slow comps threshold, v cb(slow) = 50mv, and occurs should a load current fault condition exist for more than 18 m s. the current level at which the electronic circuit breaker trips is given by equation 8: i v r mv r trip slow cb slow sense sense () () == 50 (8) the second trip point is set by the fast comps threshold, v cb(fast) = 150mv, and occurs during fast load current transients that exist for 500ns or longer. the current level at which the circuit breaker trips in this case is given by equation 9: i v r mv r trip fast cb fast sense sense () () == 150 (9) as a design aid, the currents at which electronic circuit breaker trips for common values for r sense are shown in table 4. table 4. i trip(slow) and i trip(fast) vs r sense r sense i trip(slow) i trip(fast) 0.005 w 10a 30a 0.006 w 8.3a 25a 0.007 w 7.1a 21a 0.008 w 6.3a 19a 0.009 w 5.6a 17a 0.01 w 5a 15a for proper circuit breaker operation, kelvin-sense pcb connections between the sense resistor and the ltc4212s v cc and sense pins are strongly recommended. the drawing in figure 7 illustrates the correct way of making connections between the ltc4212 and the sense resistor. pcb layout should be balanced and symmetrical to mini- mize wiring errors. in addition, the pcb layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. the power rating of the sense resistor should accommo- date steady-state fault current levels so that the compo- nent is not damaged before the circuit breaker trips. table 5 in the appendix lists sense resistors that can be used with the ltc4212s circuit breaker. calculating circuit breaker trip current for a selected r sense value, the nominal load current that trips the circuit breaker is given by equation 10: irc-tt sense resistor lr251201r010f or equivalent 0.01 , 1%, 1w current flow to load current flow to load to v cc to sense track width w: 0.03" per amp on 1 oz copper w 4212 f07 figure 7. making pcb connections to the sense resistor i v r mv r trip nom cb nom sense nom sense nom () () () () == 50 (10) the minimum load current that trips the circuit breaker is given by equation 11. i v r mv r trip min cb min sense max sense max () () () () == 40 (11) where rr r sense max sense nom tol () () =+ ? ? ? ? ? ? 1 100 the maximum load current that trips the circuit breaker is given in equation 12. i v r mv r trip max cb max sense min sense min () () () () == 60 (12) where rr r sense min sense nom tol () ( ) = ? ? ? ? ? ? 1 100
21 ltc4212 4212f operatio u for example: if a sense resistor with 7m w 5% r tol is used for current limiting, the nominal trip current i trip(nom) = 7.1a. from equations 11 and 12, i trip(min) = 5.4a and i trip(max) = 9.02a respectively. for proper operation and to avoid the circuit breaker tripping unnecessarily, the minimum trip current (i trip(min) ) must exceed the circuits maximum operating load current. for reliability purposes, the operation at the maximum trip current (i trip(max) ) must be evaluated carefully. if necessary, two resistors with the same r tol can be connected in parallel to yield an r sense(nom) value that fits the circuit requirements. power mosfet selection criteria to start the power mosfet selection process, choose the maximum drain-to-source voltage, v ds(max) , and the maximum drain current, i d(max) of the mosfet. the v ds(max) rating must exceed the maximum input supply voltage (including surges, spikes, ringing, etc.) and the i d(max) rating must exceed the maximum short-circuit current in the system during a fault condition. in addition, consider three other key parameters: 1) the required gate- source (v gs ) voltage drive, 2) the voltage drop across the drain-to-source on resistance, r ds(on) and 3) the maxi- mum junction temperature rating of the mosfet. power mosfets are classified into two categories: stan- dard mosfets (r ds(on) specified at v gs = 10v) and logic-level mosfets (r ds(on) specified at v gs = 5v). the absolute maximum rating for v gs is typically 20v for standard mosfets. however, the v gs maximum rating for logic-level mosfets ranges from 8v to 20v de- pending upon the manufacturer and the specific part number. the ltc4212s gate overdrive as a function of v cc is illustrated in the typical performance curves. logic- level mosfets are recommended for low supply voltage applications and standard mosfets can be used for appli- cations where supply voltage is greater than 4.75v. note that in some applications, the gate of the external mosfet can discharge faster than the output voltage when the circuit breaker is tripped. this causes a negative v gs voltage on the external mosfet. usually, the selected external mosfet should have a v gs(max) rating that is higher than the operating input supply voltage to ensure that the external mosfet is not destroyed by a negative v gs voltage. in addition, the v gs(max) rating of the mosfet must be higher than the gate overdrive voltage. lower v gs(max) rating mosfets can be used with the ltc4212 if the gate overdrive is clamped to a lower voltage. the circuit in figure 8 illustrates the use of zener diodes to clamp the ltc4212s gate overdrive signal if lower voltage mosfets are used. v cc v out *user selected voltage clamp (a low bias current zener diode is recommended) 1n4688 (5v) 1n4692 (7v): logic-level mosfet 1n4695 (9v) 1n4702 (15v): standard-level mosfet 4212 f08 r sense gate d2* d1* q1 r g 200 figure 8. optional gate clamp for lower v gs(max) mosfets the r ds(on) of the external pass transistor should be low to make its drain-source voltage (v ds ) a small percentage of v cc . at a v cc = 2.5v, v ds + v rsense = 0.1v yields 4% error at the output voltage. this restricts the choice of mosfets to very low r ds(on) . at higher v cc voltages, the v ds requirement can be relaxed in which case mosfet package dissipation (p d and t j ) may limit the value of r ds(on) . table 6 lists some power mosfets that can be used with the ltc4212. for reliable circuit operation, the maximum junction tem- perature (t j(max) ) for a power mosfet should not exceed the manufacturers recommended value. this includes normal mode operation, start-up, current-limit and autoretry mode in a fault condition. under normal condi- tions the junction temperature of a power mosfet is given by equation 13: mosfet junction temperature, t j(max) t a(max) + q ja ? p d (13)
22 ltc4212 4212f table 5 lists some current sense resistors that can be used with the circuit breaker. table 6 lists some power mosfets that are available. table 7 lists the web sites of several manufacturers. since this information is subject to change, please verify the part numbers with the manufacturer. operatio u where p d = (i load ) 2 ? r ds(on) q ja = junction-to-ambient thermal resistance t a(max) = maximum ambient temperature if a short circuit happens during start-up, the external mosfet can experience a big single pulse energy. this is especially true if the applications only employed a small gate capacitor or no gate capacitor at all. consult the safe operating area (soa) curve of the selected mosfet to ensure that the t j(max) is not exceeded during start-up. using staggered pin connectors the ltc4212 can be used on either a printed circuit board or on the backplane side of the connector. printed circuit board edge connectors with staggered pins are recom- mended as the insertion and removal of circuit boards do sequence the pin connections. supply voltage and ground connections on the printed circuit board should be wired to the edge connectors long pins or blades. control and status signals (like fault and on) passing through the cards edge connector should be wired to short length pins or blades. pcb connection sense there are a number of ways to use the ltc4212s on pin to detect whether the printed circuit board has been fully seated in the backplane before the ltc4212 commences a start-up cycle. an example is shown in the schematic on the front page of this data sheet. in this case, the ltc4212 is mounted on the pcb and a 20k/10k resistive divider is connected to the on pin. on the edge connector, r1 is wired to a short pin. until the connectors are fully mated, the on pin is held low, keeping the ltc4212 in an off state. once the connectors are mated, the resistive divider is con nected to v cc , v on > 1.316v and the ltc4212 begins a start-up cycle. pcb layout considerations for proper operation of the ltc4212s circuit breaker function, a 4-wire kelvin connection to the sense resistors is highly recommended. in hot swap applications where load currents can reach 10a or more, narrow pcb tracks exhibit more resistance than wider tracks and operate at more elevated temperatures. since the sheet resistance of 1 ounce copper foil is approximately 0.54m w /square, track resistances add up quickly in high current applica- tions. thus, to keep pcb track resistance and temperature rise to a minimum, pcb track width must be appropriately sized. consult appendix a of ltc application note 69 for details on sizing and calculating trace resistances as a function of copper thickness. in the majority of applications, it will be necessary to use plated-through vias to make circuit connections from component layers to power and ground layers internal to the pc board. for 1 ounce copper foil plating, a good starting point is 1a of dc current per via, making sure the via is properly dimensioned so that solder completely fills any void. for other plating thicknesses, check with your pcb fabrication facility. appe dix u table 5. sense resistor selection guide current limit value part number description manufacturer 1a lr120601r050 0.05 w 0.5w 1% resistor irc-tt 2a lr120601r025 0.025 w 0.5w 1% resistor irc-tt 2.5a lr120601r020 0.02 w 0.5w 1% resistor irc-tt 3.3a wsl2512r015f 0.015 w 1w 1% resistor vishay-dale 5a lr251201r010f 0.01 w 1.5w 1% resistor irc-tt 10a wsr2r005f 0.005 w 2w 1% resistor vishay-dale
23 ltc4212 4212f table 6. n-channel selection guide current level (a) part number description manufacturer 0 to 2 mmdf3n02hd dual n-channel so-8 on semiconductor r ds(on) = 0.1 w , c iss = 455pf 2 to 5 mmsf5n02hd single n-channel so-8 on semiconductor r ds(on) = 0.025 w , c iss = 1130pf 5 to 10 mtb50n06v single n-channel dd pak on semiconductor r ds(on) = 0.028 w , c iss = 1570pf 10 to 20 mtb75n05hd single n-channel dd pak on semiconductor r ds(on) = 0.0095 w , c iss = 2600pf table 7. manufacturers web sites manufacturer web site temic semiconductor www.temic.com international rectifier www.irf.com on semiconductor www.onsemi.com harris semiconductor www.semi.harris.com irc-tt www.irctt.com vishay-dale www.vishay.com vishay-siliconix www.vishay.com diodes, inc. www.diodes.com appe dix u u package descriptio ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) msop (ms) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C 0.27 (.007 C .011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24 ltc4212 4212f lt/tp 0304 1k ? printed in usa ? linear technology corporation 2003 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts part number description comments ltc1421 two channels, hot swap controller operates from 3v to 12v and supports C 12v ltc1422 single channel, hot swap controller operates from 2.7v to 12v lt1640al/lt1640ah negative voltage hot swap controller operates from C10v to C80v ltc1642 single channel, hot swap controller overvoltage protection and foldback current limit ltc1643al/ltc1643ah pci-bus hot swap controller 3.3v, 5v and 12v for pci and cpci ltc1647 dual channel, hot swap controller operates from 2.7v to 16.5v ltc4210-1/ltc4210-2 single channel, hot swap controller hot swap controller with active current limiting ltc4211 single channel, hot swap controller overvoltage and overcurrent protection ltc4230 triple channel, hot swap controller triple hot swap controller with multifunction current control ltc4241 pci-bus hot swap controller with 3.3v auxiliary standby channel ltc4251/ltc4251-1/ C48v voltage hot swap controller negative voltage hot swap controller in sot-23 ltc4251-2 ltc4252 C48v hot swap controller C48v hot swap controller in 8-pin or 10-pin msop ltc4253 triple power supply sequenced C48v hot swap controller C48v hot swap controller with triple supply sequencing in 16-pin ssop lt4256-1/lt4256-2 positive voltage hot swap controller operates from 10.8v to 80v, autoretry/latch off + v cc sense ltc4212 9 1 10 23 87 10 f + 10 f 2 3 1 5v 2.5v 1.5a 3.3v 1.5a 4212 ta02 6 gate pgt 4 pgf timer c timer 0.01 f pgi on v cc 5v gnd z1 = smaj10a (tvs) r x 10 r sense 0.007 edge connector (male) m1 si4410dy z1 r4 10k r6 2.1k r5 10k fault gnd fault + 10 f lt1963-2.5 c pgt 180nf c pgf 18pf c x 100nf backplane connector (female) 5 + 10 f 2 3 1 + 10 f lt1963-3.3 4 3 ltc1326-2.5 gnd v cca 1 v cc3 6 rst 2 v cc25 r2 20k r1 10k r3 10k typical applicatio u monitoring dc/dc converters with the ltc1326-2.5 supply monitor

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